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This paper describes an approach to explore the design space for architectures of packet processing devices on the system level. The method is specific to the application domain of packet processors and is based on models for packet processing tasks, a specification of the workload generated by traffic streams, and a description of the feasible space of architectures including computation and communication resources, a measure to characterize the performance of network processors under different usage scenarios, a new method to estimate end-to-end packet delays and queuing memory, taking task scheduling policies and bus arbitration schemes into account, and a evolutionary algorithm for multi-objective design space exploration.

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Format:PDFSize:583 KB
Date:Jan 2008
Pages:12

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