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In this paper, the design and verification of a Clock and Data Recovery circuit (CDR) is presented. The circuit is designed and verified at 90-nm digital CMOS platform of ST Microelectronics and complies with the requirements of Bellcore GR-253 SONET OC-12 standard. The CDR system consists of a Phase Locked Loop (PLL) based dual loop architecture which includes a phase detector, a phase-frequency detector, two charge pumps, a low-pass filter, a Voltage Controlled Oscillator (VCO) and a feedback divider. Due to the use of dual loop architecture, a lock detect circuitry is required. Also, a power down circuitry is designed for determining which of the loops to operate under desired conditions. The final circuit meets and exceeds SONET OC-12 jitter specifications.

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Format:PDFSize:263 KB
Date:Jun 2007
Pages:4

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