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Reconfigurable computing has emerged as a key technology in the field of high performance and embedded computing. This research focuses on the use of reconfigurable processors for solving computationally intensive scientific applications, with an added twist. An architecture is designing that can retarget its resources dynamically based on run-time and data-driven variation in task level parallelism, as typically seen in radar-based target tracking, high performance video compression, and N-body simulations. The approach advocates the derivation of such runtime-reconfigurable architectures through a set of compile time analyses, integrating resource derivation and allocation with a set of architectural features that permit rapid run-time adaptation of reconfigurable data paths.

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Format:PDFSize:90 KB
Date:Dec 2006
Pages:2

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