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Overview:

This paper introduces two different physical structures and topologies to realize an ethernet layer-2 switch. To evaluate these two structures and produce throughput projections the paper has utilized MPI. This simulation environment has helped to identify performance bottlenecks and to give an overall estimation of the switch throughput. The results show that for a hardware implementation of this switch in .18um technology, assuming a 200 MHz clock rate for the processing elements and 100 MHz clock rate for the memory blocks, the design can support multiple gigabit channel ports.

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Format:PDFSize:81 KB
Date:Jan 2008
Pages:7

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