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Overview:

This paper describes the design, implementation, and experimental evaluation of a reconfigurable network processor that can do on-the-fly content adaptation of IP packets for wired or wireless networks. In the demonstration application, FPGA technology is used in conjunction with traditional RISC micro-processors to perform IP packet compression in hard-ware, using a CAM-based hardware implementation of the Lempel-Ziv (LZ) compression algorithm. The experimental evaluation considers HTTP Web browsing traffic using the TCP/IP protocols. The measurement results show that the proposed LZ compression architecture can reduce network byte traffic volume by 5- 38%. Furthermore, the hardware-based approach pro-vides consistent throughput performance as the compression buffer size is increased.

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Format:PDFSize:200 KB
Date:Jan 2007
Pages:10

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